Conventional non-volatile memory (NVM) cells are routinely used in electronic circuitry, such as electronic consumer devices. A typical non-volatile memory cell often includes multiple transistors with a floating gate. A charge stored on the floating gate typically represents the logical value stored in the non-volatile memory cell.
Conventional non-volatile memory cells often suffer from a problem known as over-erasure. Over-erasure occurs when the floating gate of a non-volatile memory cell is positively charged during an erasure of the non-volatile memory cell. This positive charge could prevent subsequent programming of the non-volatile memory cell. This positive charge could also allow only a weak subsequent programming of the non-volatile memory cell, meaning the non-volatile memory cell provides a less-than-expected current after programming (which makes it more difficult to determine the programming state of the memory cell). Either of these problems may lead to a program failure of the non-volatile memory cell.
While various techniques have been developed to combat over-erasure, production irregularities associated with the non-volatile memory cells make it difficult to define a uniform erase procedure. One example production irregularity is the variations in charges held by the floating gates in non-volatile memory cells after fabrication. Other example production irregularities include variations in the transistor threshold voltages, gate oxide thicknesses, and doping concentrations in the non-volatile memory cells.
Solutions have been proposed to inhibit over-erasure while considering such production irregularities. However, these solutions typically require additional components, which increase the cost of the memory cells. These solutions also often optimize each individual memory cell's erase condition, which typically makes the erase time too long for use with large-scale memory cell arrays. In addition, these solutions often do not work when attempting to erase an entire memory cell array or when attempting to erase a memory cell array block-by-block because the memory state distribution (how many cells are in the “0” state and how many cells are in the “1” state) is unpredictable before the erase operation.
Another technique for combating over-erasure involves applying a larger programming voltage to the source of a program transistor in a non-volatile memory cell. A particular example could involve a 40% increase over a normal programming voltage, such as 7V compared to a 5V normal programming voltage. However, this results in higher power consumption by the non-volatile memory cell. This technique is also not immune to production irregularities associated with the non-volatile memory cells.